Landing: ea1a75bfd580
Project / Subsystem
gcc / gcc/risc-v
Date
2026-07-02
Author
Jeff Law
Commit
ea1a75bfd580788b6c1f0a772051797bbddedf82
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/risc-v
- patch_id
- —
- commit_hash
- ea1a75bfd580788b6c1f0a772051797bbddedf82
- source_type
- github
- headline
- RISC-V ADD synthesis exploits new instructions and costs.
- tldr
- RISC-V compiler can now synthesize ADD instructions more efficiently using new patterns and cost models.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • compiler
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-02T00:00:00.000Z
GCC’s RISC-V backend gains improved ADD instruction synthesis. It now leverages the add.uw instruction for specific constant patterns and recognizes INT_MIN additions as a binvi operation. This change also refactors the cost model to use riscv_integer_cost over riscv_const_insns, enabling better selection of cheaper instructions when multiple options exist.