Landing: af13bb056c65
Project / Subsystem
gcc / gcc
Date
2026-07-03
Author
Jeff Law
Commit
af13bb056c65532fc4b3cecd06f51f82a7c70149
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- af13bb056c65532fc4b3cecd06f51f82a7c70149
- source_type
- github
- headline
- Improve AND synthesis
- tldr
- Enhances RISC-V AND instruction synthesis using integer cost heuristics and rotation operations.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • RISC-V
- • optimization
- • code generation
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-03T00:00:00.000Z
This commit improves the synthesis of AND operations for RISC-V architectures by changing the cost heuristic from riscv_const_insns to riscv_integer_cost, aligning it with similar optimizations for XOR and OR operations. Additionally, it introduces a new optimization that utilizes rotation instructions combined with bit clearing for constants with sparse set bits, improving code generation for cases like x & 0xff000000000000ff.