Landing: 30fa32b2bff3
Project / Subsystem
gcc / gcc/risc-v
Date
2026-07-06
Author
Jim Lin
Commit
30fa32b2bff36d7b63fccdc997bd5f51b1427308
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/risc-v
- patch_id
- —
- commit_hash
- 30fa32b2bff36d7b63fccdc997bd5f51b1427308
- source_type
- github
- headline
- RISC-V test fixes: sign extension shift amount and -Og skip
- tldr
- Two RISC-V test suite corrections: one for sign extension checks and another for skipping a test under -Og.
- author
- Jim Lin
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • gcc
- • testsuite
- • compiler
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-06T00:00:00.000Z
This commit includes two fixes for the RISC-V test suite. First, ext-dce-4.c is updated to use a shift amount of 4 instead of 8 in test_half_sign_needed. This ensures the test correctly expects a lh (load halfword) instruction, rather than a lb (load byte), for sign-extending halfword loads. Second, shift-shift-7.c is now skipped when compiled with the -Og optimization level. This prevents a regex matching failure that occurs because -Og preserves shifts as separate instructions, causing conflicts with the test’s assembly scan.