Landing: 3f2b3eced0f8
Project / Subsystem
gcc / i386
Date
2026-07-07
Author
liuhongt
Commit
3f2b3eced0f8278fa335b1337a98b96df3ea062e
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- i386
- patch_id
- —
- commit_hash
- 3f2b3eced0f8278fa335b1337a98b96df3ea062e
- source_type
- github
- headline
- i386: Prefer shorter fold-left reduction chains
- tldr
- Improve loop vectorization cost model for FP reductions on x86.
- author
- liuhongt
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • i386
- • vectorization
- • optimization
- • cost-model
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-07T00:00:00.000Z
This commit enhances the i386 vectorization cost model to prefer shorter instruction chains for floating-point reductions. Previously, wider vector modes could be chosen even if they increased the serial reduction chain length, impacting performance. The changes introduce a new metric to count reduction lanes, influencing loop candidate selection and preventing emulated sub-SSE modes from winning solely on this preference.