Landing: 98fa7681e728

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Project / Subsystem

gcc / risc-v

Date

2026-07-07

Author

Pan Li

Commit

98fa7681e728cf6331bd519034f14a48227a5b26

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 98fa7681e728cf6331bd519034f14a48227a5b26
source_type: github
headline: RISC-V: Allow RVV register overlap for v[sz]ext.vf2
tldr: Enables RISC-V compiler to consider register overlap for widening vector instructions.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector extension
• optimization
• register allocation
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/98fa7681e728cf6331bd519034f14a48227a5b26
date: 2026-07-07T00:00:00.000Z

This commit updates the RISC-V backend to allow for register overlap in widening operations like vzext.vf2 and vsext.vf2, conforming to the RVV 1.0 specification. It renames constraints and adjusts register allocation logic to consider available overlapping register pairs, improving potential register utilization.