Landing: 25331f87bfbd
Project / Subsystem
gcc / gcc/risc-v
Date
2026-07-08
Author
Pan Li
Commit
25331f87bfbd81305b2568a5f9c0fdb568b36b14
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/risc-v
- patch_id
- —
- commit_hash
- 25331f87bfbd81305b2568a5f9c0fdb568b36b14
- source_type
- github
- headline
- RISC-V: RVV register overlap allowed for v[sz]ext.vf4
- tldr
- RISC-V vector extension now permits register overlap for `(v)sext.vf4` instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector extension
- • register allocation
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-08T00:00:00.000Z
This commit modifies the RISC-V vector implementation to allow register overlap for vzext.vf4 and vsext.vf4 instructions, similar to how it’s handled for v[sz]ext.vf2. This change involves adding a new predicate function is_frac_vlmul_p and updating the riscv_v_widen_constraint_ok function and vector machine description to accommodate these overlapping register constraints.