Landing: 7af6db6d7b59

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Project / Subsystem

gcc / gcc/risc-v

Date

2026-07-08

Author

Pan Li

Commit

7af6db6d7b5903c118f9cc57ff2496128c78f518

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: gcc/risc-v
patch_id: —
commit_hash: 7af6db6d7b5903c118f9cc57ff2496128c78f518
source_type: github
headline: RISC-V: New test cases for vsext.vf4 register overlap
tldr: Added RISC-V test cases for `vsext.vf4` to verify register group overlap behavior.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• testsuite
• vector extension
• register allocation
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/7af6db6d7b5903c118f9cc57ff2496128c78f518
date: 2026-07-08T00:00:00.000Z

This commit adds a set of new test cases for the RISC-V vector instruction vsext.vf4. These tests are designed to check for correct behavior when the destination registers for vsext.vf4 operations overlap with subsequent registers, particularly across different vector element widths and mask factors.