Landing: 83b0befb611a
Project / Subsystem
gcc / gcc/riscv
Date
2026-07-08
Author
Jim Lin
Commit
83b0befb611af61e0b4efbbc0ee235fe773ae891
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/riscv
- patch_id
- —
- commit_hash
- 83b0befb611af61e0b4efbbc0ee235fe773ae891
- source_type
- github
- headline
- RISC-V: Fix dead cpop reservation for spacemit-x60
- tldr
- Corrects a RISC-V instruction scheduling bug where the cpop instruction was not using its intended latency.
- author
- Jim Lin
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • scheduling
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-08T00:00:00.000Z
This commit fixes a bug in the RISC-V backend where the ‘cpop’ instruction was incorrectly assigned a latency of 1 due to a flawed reservation definition. It was being matched by a more general ALU reservation, leaving a dedicated 2-cycle reservation unused. By removing ‘cpop’ from the general ALU reservation, the compiler now correctly schedules it with its intended 2-cycle latency.