Landing: bfc82936d1ea

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Project / Subsystem

gcc / risc-v

Date

2026-07-11

Author

Jin Ma

Commit

bfc82936d1ea078d21a58e063fd27022371ca3a3

Source

github

Perf win

Breaking

Yes

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: bfc82936d1ea078d21a58e063fd27022371ca3a3
source_type: github
headline: RISC-V excludes t1 from sibcall registers to prevent overwrites
tldr: RISC-V's t1 register is now excluded from sibcall register sets to prevent overwrites by RVV epilogues, ensuring correct indirect sibcall execution.
author: Jin Ma
outcome: committed
performance_win: false
breaking_change: true
series_id: —
series_parts: []
tags: • risc-v
• register-allocation
• rvv
• bugfix
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/bfc82936d1ea078d21a58e063fd27022371ca3a3
date: 2026-07-11T00:00:00.000Z

The t1 register on RISC-V has been excluded from the SIBCALL_REGS set and mapped to JALR_REGS. This change prevents an indirect sibcall target stored in t1 from being overwritten by the RVV (RISC-V Vector) scalable-frame epilogue before the final jump. Test cases are updated to reflect this register class change.