Landing: d440d4eeae8a

← All landings

Project / Subsystem

gcc / risc-v

Date

2026-07-11

Author

Pan Li

Commit

d440d4eeae8a3b295403684c3d34c8d961704950

Source

github

Perf win

Yes

Breaking

View on GitHub →

All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: d440d4eeae8a3b295403684c3d34c8d961704950
source_type: github
headline: RISC-V: Allow RVV register overlap for v[sz]ext.vf8
tldr: Enables register overlap for RISC-V vector instructions v[sz]ext.vf8, similar to v[sz]ext.vf4.
author: Pan Li
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/d440d4eeae8a3b295403684c3d34c8d961704950
date: 2026-07-11T00:00:00.000Z

The RISC-V vector extension (RVV) code generator has been updated to permit register overlap for the v[sz]ext.vf8 instructions. This change mirrors the behavior already implemented for v[sz]ext.vf4 and utilizes the Wvr constraint in the vector machine description to manage register usage.