Landing: f1c03c18ef6f
Project / Subsystem
gcc / risc-v
Date
2026-07-11
Author
Pan Li
Commit
f1c03c18ef6f229bffb6da1834b80031b72fbc84
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- f1c03c18ef6f229bffb6da1834b80031b72fbc84
- source_type
- github
- headline
- RISC-V: Add test cases for vsext.vf8 reg overlap
- tldr
- New tests are added to verify register group overlap for RISC-V vsext.vf8 vector instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • test
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-11T00:00:00.000Z
Four new RISC-V test cases have been introduced to assess register group overlap with the vsext.vf8 instruction. These tests cover scenarios with signed 8-bit integers and various multiplier configurations (m1, mf2, mf4, mf8), ensuring correct handling of register usage during compilation.