Landing: 5d98400b5a77
Project / Subsystem
gcc / gcc/vector
Date
2026-07-15
Author
Pan Li
Commit
5d98400b5a77795c5103dbfe3f4a19f51c04f4c6
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/vector
- patch_id
- —
- commit_hash
- 5d98400b5a77795c5103dbfe3f4a19f51c04f4c6
- source_type
- github
- headline
- RISC-V: Align vwcvt[u].x.x.v with vsext.vf8 register overlap rules
- tldr
- RISC-V vector extension allows register overlap for vwcvt[u].x.x.v instructions, similar to vsext.vf8.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector extension
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-15T00:00:00.000Z
This change allows the RISC-V vector extension’s vwcvt[u].x.x.v instructions to utilize register overlap. By leveraging the Wvr constraint in the vector instruction definition, the compiler can now generate code where the destination vector register set overlaps with the source register set, similar to the existing behavior of v[sz]ext.vf8.