Landing: df635aadf0f3
Project / Subsystem
gcc / risc-v
Date
2026-07-15
Author
Pan Li
Commit
df635aadf0f3845377dab5690c3c394862f4a836
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- df635aadf0f3845377dab5690c3c394862f4a836
- source_type
- github
- headline
- RISC-V: Add test cases for vwcvtu.x.x.v reg overlap
- tldr
- New RISC-V test cases added to verify register group overlap for vwcvtu.x.x.v instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • testing
- • vector
- • autovectorization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-15T00:00:00.000Z
This commit introduces a suite of new test cases for the RISC-V Vector Extension, specifically focusing on the vwcvtu.x.x.v instruction. These tests are designed to evaluate scenarios involving register group overlap during the execution of these vector conversion instructions, ensuring correct behavior when different vector register groups are utilized.