Landing: 13fa720ce146
Project / Subsystem
gcc / risc-v
Date
2026-07-16
Author
Pan Li
Commit
13fa720ce146b00199ec7a8c5854efd6b0c1f101
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 13fa720ce146b00199ec7a8c5854efd6b0c1f101
- source_type
- github
- headline
- RISC-V: Allow vector register overlap for vfwcvt.x[u].f.v.
- tldr
- RISC-V vector conversion instructions now support register overlap.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-16T00:00:00.000Z
This change enables register group overlap for the RISC-V vector instructions vfwcvt.x.f.v and vfwcvt.xu.f.v. Similar to the existing support for v[sz]ext.vf8, this allows the destination register group to overlap with the source register group. This modification is implemented by leveraging the Wvr constraint in the vector.md configuration, facilitating more flexible and potentially efficient register allocation for these conversion operations.