Landing: b460a877061a

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Project / Subsystem

gcc / risc-v

Date

2026-07-16

Author

Jin Ma

Commit

b460a877061a71daeed6f7fca01b8274d9fdd9da

Source

github

Perf win

Yes

Breaking

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project: gcc
subsystem: risc-v
patch_id: —
commit_hash: b460a877061a71daeed6f7fca01b8274d9fdd9da
source_type: github
headline: RISC-V uses pseudo-register for sibcall addresses
tldr: RISC-V compiler now uses a pseudo-register for sibcall addresses to improve optimization and avoid unnecessary reloads.
author: Jin Ma
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• optimization
• register-allocation
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/b460a877061a71daeed6f7fca01b8274d9fdd9da
date: 2026-07-16T00:00:00.000Z

The RISC-V compiler has been modified to use a pseudo-register for materializing sibcall addresses. This change allows the register allocator (LRA) to directly select registers suitable for sibcalls, preventing a potential reload of a temporary register (t1) that is needed for normal calls. This is an optimization that ensures sibcalls are handled correctly without interference.