Landing: c33b7b995f9c
Project / Subsystem
gcc / risc-v
Date
2026-07-16
Author
Pan Li
Commit
c33b7b995f9c932182cc54032b4a747b54070fc6
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- c33b7b995f9c932182cc54032b4a747b54070fc6
- source_type
- github
- headline
- RISC-V: Add tests for vfwcvtu.xu.f.v register group overlap.
- tldr
- New RISC-V tests cover register group overlap for vfwcvtu.xu.f.v.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • test
- • vector
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-16T00:00:00.000Z
This commit introduces a suite of new test cases for RISC-V vector operations, specifically focusing on the vfwcvtu.xu.f.v instruction. These tests exercise register group overlap scenarios with various data types (f16, f32) and vector lengths (m1, m2, m4, mf2, mf4). The inclusion of these tests aims to ensure the correct handling of register allocation and data flow when vector registers are reused within these conversion operations.