Landing: fc3efdeb72ac
Project / Subsystem
gcc / risc-v
Date
2026-07-16
Author
Pan Li
Commit
fc3efdeb72acb145a5a4772d88a2367eef535edf
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- fc3efdeb72acb145a5a4772d88a2367eef535edf
- source_type
- github
- headline
- RISC-V: Add tests for vfcvt.x.f.v register group overlap.
- tldr
- New RISC-V tests cover register group overlap for vfcvt.x.f.v.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • test
- • vector
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-16T00:00:00.000Z
This commit introduces a series of new test cases for the RISC-V vector instruction vfwcvt.x.f.v. These tests focus on scenarios involving register group overlap, where destination registers might coincide with source registers. The tests cover various data types including f16 and f32, and different vector lengths, ensuring the compiler correctly handles these potentially complex register allocation situations.