Landing: ec58d736cd57

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Project / Subsystem

gcc / expand

Date

2026-07-17

Author

Robin Dapp

Commit

ec58d736cd572bb01cfba986f090ab42f195a464

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: expand
patch_id: —
commit_hash: ec58d736cd572bb01cfba986f090ab42f195a464
source_type: github
headline: expand: Handle non-word addressable modes for vector registers.
tldr: Compiler can now handle non-word addressable modes for vector registers by spilling to memory or requiring target-specific move patterns.
author: Robin Dapp
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• risc-v
• compiler
• vectorization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/ec58d736cd572bb01cfba986f090ab42f195a464
date: 2026-07-17T00:00:00.000Z

The compiler’s expand pass now correctly handles non-word addressable modes for vector registers, crucial for targets like aarch64 and riscv where a vector register’s natural size might exceed the word size. It achieves this by spilling unsplittable modes to memory or by deferring to extract_bit_field. Additionally, targets are now required to provide integer move patterns for modes up to REGMODE_NATURAL_SIZE to avoid expansion progress issues.