Landing: 53c4e6602ac7
Project / Subsystem
gcc / risc-v
Date
2026-07-19
Author
Pan Li
Commit
53c4e6602ac7bb23cc6f873e59578840f15575db
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 53c4e6602ac7bb23cc6f873e59578840f15575db
- source_type
- github
- headline
- RISC-V: Enable register overlap for vfwcvt.f.f.v vector instruction.
- tldr
- RISC-V backend now allows register overlap for the vfwcvt.f.f.v vector instruction.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • rvv
- • vector
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-19T00:00:00.000Z
This commit updates the RISC-V backend to permit register overlap for the vfwcvt.f.f.v vector instruction. Similar to how vsext.vf8 and overlay.vf8 handle register reuse, this change allows the compiler to more efficiently schedule vector operations. By leveraging the Wvr constraint in the machine description, the backend can now better utilize available registers when generating code for this specific widen-converting floating-point vector instruction.