Landing: ebca3fd0efc8
Project / Subsystem
gcc / risc-v
Date
2026-07-19
Author
Pan Li
Commit
ebca3fd0efc881ad033a7a8da6e7f254edfca26c
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- ebca3fd0efc881ad033a7a8da6e7f254edfca26c
- source_type
- github
- headline
- RISC-V: Add test cases for vector float conversion register overlap.
- tldr
- New tests verify register group overlap handling for RVV's vfwcvt.f.f.v instruction.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • rvv
- • vector
- • testsuite
- • floating-point
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-19T00:00:00.000Z
This commit introduces a suite of new test cases for the RISC-V Vector (RVV) extension, specifically focusing on the vfwcvt.f.f.v instruction. These tests aim to validate the correct handling of register group overlap, a scenario where instruction operands might share register resources. The addition of these tests ensures the compiler properly manages register allocation and avoids conflicts when generating code for this vector floating-point conversion instruction across various vector lengths and element sizes.