Landing: b6bebf2a7326
Project / Subsystem
gcc / gcc/target/riscv
Date
2026-07-20
Author
Shreya Munnangi
Commit
b6bebf2a7326e6b5566f1aa2979233a60e5c8377
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/target/riscv
- patch_id
- —
- commit_hash
- b6bebf2a7326e6b5566f1aa2979233a60e5c8377
- source_type
- github
- headline
- RISC-V atomic load sequences improved
- tldr
- RISC-V atomic load sequences are optimized to remove redundant instructions and improve constraint handling.
- author
- Shreya Munnangi
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • atomic
- discussion_id_link
- github:gcc-mirror/gcc#124741
- bugzilla_pr
- —
- date
- 2026-07-20T00:00:00.000Z
This commit optimizes atomic load sequences on RISC-V architectures, particularly for RV64. It eliminates redundant sign extensions and improves address arithmetic. New constraints and iterators are introduced to correctly handle memory model acquire semantics and target-specific features like ZALRSC, ensuring generated code is more efficient and correct across different configurations.