Landing: 0eb5dc76092a
Project / Subsystem
gcc / risc-v
Date
2026-07-20
Author
Pan Li
Commit
0eb5dc76092a6e85738f323195d65a4731cec180
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 0eb5dc76092a6e85738f323195d65a4731cec180
- source_type
- github
- headline
- Add RISC-V RVV test cases for vfwcvt.f.xu.v register group overlap
- tldr
- New RISC-V test cases are added to cover register group overlap scenarios for the `vfwcvt.f.xu.v` instruction.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • rvv
- • compiler
- • test
- • vector
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-20T00:00:00.000Z
This commit introduces a suite of new test cases for the RISC-V Vector extension, specifically targeting the vfwcvt.f.xu.v instruction. The tests focus on scenarios involving register group overlap, exploring various data types (u8, u16, u32) and vector lengths (m1, m2, m4, mf2, mf4, mf8). These additions aim to ensure correct behavior and compiler support for these overlap configurations.