Landing: d52709668a7f
Project / Subsystem
gcc / risc-v
Date
2026-07-20
Author
Pan Li
Commit
d52709668a7fe7b22e2c3734e0bebf67faaef29a
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- d52709668a7fe7b22e2c3734e0bebf67faaef29a
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vfwcvt.f.x[u] instructions
- tldr
- The RISC-V Vector extension now allows register overlap for `vfwcvt.f.x.v` and `vfwcvt.f.xu.v` instructions, improving flexibility in register allocation.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • rvv
- • compiler
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-20T00:00:00.000Z
The GCC RISC-V backend now permits register overlap for the vfwcvt.f.x.v and vfwcvt.f.xu.v instructions. This change mirrors similar allowances for other vector instructions like vsext.vf8 and vszext.vf8, providing the compiler with more flexibility in register allocation and potentially enabling more efficient code generation for these vector conversion operations.