Landing: e43b9a1fc78b
Project / Subsystem
gcc / risc-v
Date
2026-07-20
Author
Pan Li
Commit
e43b9a1fc78ba84caa89e455baad35d8e7440502
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- e43b9a1fc78ba84caa89e455baad35d8e7440502
- source_type
- github
- headline
- Add RISC-V RVV test cases for vfwcvt.f.x.v register group overlap
- tldr
- New RISC-V test cases are added to cover register group overlap scenarios for the `vfwcvt.f.x.v` instruction.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • rvv
- • compiler
- • test
- • vector
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-20T00:00:00.000Z
This commit introduces a comprehensive set of new test cases for the RISC-V Vector extension, focusing on the vfwcvt.f.x.v instruction. These tests specifically explore register group overlap across various data types (i8, i16, i32) and vector lengths (m1, m2, m4, mf2, mf4, mf8). The goal is to validate the compiler’s handling of these overlap conditions for signed integer to floating-point conversions.