Landing: a4cb95eacb36
Project / Subsystem
gcc / risc-v
Date
2026-07-22
Author
Pan Li
Commit
a4cb95eacb360531a7ff843f1a833d34cecdb6ba
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- a4cb95eacb360531a7ff843f1a833d34cecdb6ba
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vfwcvt.rtz.x[u].f.v
- tldr
- RISC-V vector instructions vfwcvt.rtz.x[u].f.v now permit register overlap.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector instructions
- • optimization
- • backend
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-22T00:00:00.000Z
The RISC-V Vector extension now allows register overlap for the vfwcvt.rtz.x[u].f.v instructions, similar to how it’s handled for v[sz]ext.vf8. This change is implemented by updating the machine description to leverage the Wvr constraint, enabling more flexible register allocation and potentially improving code generation efficiency.