Landing: a6d07f98c48b

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Project / Subsystem

gcc / risc-v

Date

2026-07-22

Author

Pan Li

Commit

a6d07f98c48bb54fcf596122ecb2ef9474fb80db

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: a6d07f98c48bb54fcf596122ecb2ef9474fb80db
source_type: github
headline: RISC-V: Add test cases for vfwcvt.rtz.xu.f.v register overlap
tldr: New RISC-V test cases verify register group overlap for vfwcvt.rtz.xu.f.v instructions.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector instructions
• testing
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/a6d07f98c48bb54fcf596122ecb2ef9474fb80db
date: 2026-07-22T00:00:00.000Z

This commit introduces a suite of new test cases for RISC-V vector operations, specifically focusing on the vfwcvt.rtz.xu.f.v instruction. The tests are designed to cover various configurations of register group overlap, ensuring the compiler correctly handles these scenarios.