Landing: ceff533bb4f3
Project / Subsystem
gcc / risc-v
Date
2026-07-23
Author
Bohan Lei
Commit
ceff533bb4f3c9a49fe30e53caef015961b56d5a
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- ceff533bb4f3c9a49fe30e53caef015961b56d5a
- source_type
- github
- headline
- RISC-V: Disallow unsupported Zvabd patterns for specific SEW.
- tldr
- Enforces Zvabd specification by disallowing unsupported SEW values for vabd/vwabda patterns.
- author
- Bohan Lei
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-23T00:00:00.000Z
This commit refines the RISC-V vector code generation to adhere strictly to the Zvabd extension’s specification. It disallows the generation of vabd and vwabda instructions for unsupported Single-Element Widths (SEW), specifically limiting them to SEW 8 or 16 as defined by the standard. This prevents the creation of invalid or non-standard vector operations.