Landing: 6427be862c76
Project / Subsystem
binutils / bfd/risc-v
Date
2026-07-24
Author
Jan Beulich <jbeulich@sourceware.org>
Commit
6427be862c76d8f82ceffd2fff3cfa6705d0d93a
Source
public_inbox
Perf win
No
Breaking
No
All attributes
- project
- binutils
- subsystem
- bfd/risc-v
- patch_id
- —
- commit_hash
- 6427be862c76d8f82ceffd2fff3cfa6705d0d93a
- source_type
- public_inbox
- headline
- RISC-V: Zvfbfwma implies Zvfbfmin
- tldr
- Ensures the RISC-V assembler correctly recognizes that the Zvfbfwma instruction implies the Zvfbfmin extension.
- author
- Jan Beulich <jbeulich@sourceware.org>
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • assembler
- • instruction sets
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-24T00:00:00.000Z
This commit updates the RISC-V assembler’s understanding of instruction subset implications. Specifically, it corrects the definition so that the Zvfbfwma instruction is recognized as implying Zvfbfmin, aligning with the RISC-V specification. This ensures correct assembly and disassembly for RISC-V code using these vector extensions.