Landing: 790c615e49d7
Project / Subsystem
binutils / risc-v
Date
2026-07-24
Author
Jan Beulich <jbeulich@sourceware.org>
Commit
790c615e49d7104abcbd4397e6ca1331181d900b
Source
public_inbox
Perf win
No
Breaking
No
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 790c615e49d7104abcbd4397e6ca1331181d900b
- source_type
- public_inbox
- headline
- RISC-V: EEW64 checking for assembler and disassembler
- tldr
- Assembler and disassembler now correctly handle RISC-V instructions using EEW64 with the Zve64x extension.
- author
- Jan Beulich <jbeulich@sourceware.org>
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector extensions
- • assembler
- • disassembler
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-24T00:00:00.000Z
This commit enhances RISC-V support by ensuring the assembler and disassembler correctly use the INSN_V_EEW64 flag. Instructions marked with this flag are now properly handled, preventing their disassembly when the Zve64x extension is not enabled. It also removes a redundant Zve32x check in the assembler, as Zve64x implicitly includes Zve32x.