Landing: 4e75c08f16fd

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Project / Subsystem

gcc / risc-v

Date

2026-07-28

Author

Jin Ma

Commit

4e75c08f16fd97c1459320738b59068f8d003500

Source

github

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Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 4e75c08f16fd97c1459320738b59068f8d003500
source_type: github
headline: RISC-V: Fix sibcall address legalization in MI thunks.
tldr: Corrects RISC-V subroutine call (sibcall) address handling in machine instruction thunks.
author: Jin Ma
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• optimization
• bugfix
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/4e75c08f16fd97c1459320738b59068f8d003500
date: 2026-07-28T00:00:00.000Z

This commit addresses an issue in the RISC-V backend where the generation of machine instruction (MI) thunks could cause an assertion failure when legalizing sibcall addresses. The problem occurred because MI thunks were generating RTL as if register allocation was complete, leading to incorrect pseudo-register creation. The fix ensures the correct register (STATIC_CHAIN_REGNUM) is used for post-reload thunk code, resolving PR126449.