Landing: 322ba88ffa34
Project / Subsystem
gcc / gcc/risc-v
Date
2026-07-30
Author
Pan Li
Commit
322ba88ffa340d841755eedd76f0f03978b77b71
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/risc-v
- patch_id
- —
- commit_hash
- 322ba88ffa340d841755eedd76f0f03978b77b71
- source_type
- github
- headline
- RISC-V: Enable RVV register overlap for vw{add,sub,mul}[u].vv instructions
- tldr
- RISC-V Vector extension now supports register overlap for widened vector add, subtract, and multiply operations.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-30T00:00:00.000Z
This commit enables register group overlap for several RISC-V Vector extension instructions: vwadd.vv, vwsub.vv, vwmul.vv, and their unsigned variants. This change allows these dual-widen vector instructions to leverage register overlap, similar to how vwadd[u].wv already does, potentially improving code density and performance.