Landing: 5f56bb4184db
Project / Subsystem
gcc / gcc/risc-v
Date
2026-07-30
Author
Pan Li
Commit
5f56bb4184dbaddcb625c8457b192305fadc3c7a
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/risc-v
- patch_id
- —
- commit_hash
- 5f56bb4184dbaddcb625c8457b192305fadc3c7a
- source_type
- github
- headline
- RISC-V: Add test cases for vwadd.vv register overlap
- tldr
- New test cases for RISC-V vwadd.vv instruction verify register group overlap for various signed integer types and widths.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-30T00:00:00.000Z
This commit introduces a comprehensive set of test cases for the RISC-V Vector extension’s vwadd.vv instruction, focusing on scenarios involving register group overlap. The tests cover signed integer types (8-bit, 16-bit, 32-bit) and various vector mask/multiplier configurations (m1, m2, m4, mf2, mf4, mf8), ensuring correct behavior when destination and source registers overlap.