Landing: ae423e262d90
Project / Subsystem
gcc / gcc/risc-v
Date
2026-07-30
Author
Pan Li
Commit
ae423e262d90bcd43fb5f6e030c19420df070131
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/risc-v
- patch_id
- —
- commit_hash
- ae423e262d90bcd43fb5f6e030c19420df070131
- source_type
- github
- headline
- RISC-V: Add test cases for unsigned vwadd.vv register overlap
- tldr
- New test cases for RISC-V vwaddu.vv instruction cover register group overlap scenarios for various data types and widths.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-07-30T00:00:00.000Z
This commit expands the test suite for the RISC-V Vector extension by adding numerous test cases for the vwaddu.vv instruction. These tests specifically target scenarios involving register group overlap across different data types (unsigned 8-bit, 16-bit, and 32-bit) and various vector mask/multiplier configurations (m1, m2, m4, mf2, mf4, mf8).