Landing: 41b68b76bc71
Project / Subsystem
gcc / risc-v
Date
2026-08-01
Author
Pan Li
Commit
41b68b76bc718733bb501e7f4a0afc1ec57db8d0
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 41b68b76bc718733bb501e7f4a0afc1ec57db8d0
- source_type
- github
- headline
- RISC-V: Add test cases for vwsubu.vv register overlap
- tldr
- New test cases verify register overlap behavior for RISC-V vwsubu.vv vector instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-01T00:00:00.000Z
This commit adds a suite of test cases to verify the behavior of the vwsubu.vv (unsigned widening subtract) RISC-V vector instruction when register groups overlap. The tests cover various data types and vector lengths to ensure correct operation under these specific conditions.