Landing: c55a61e3cdb4

← All landings

Project / Subsystem

gcc / risc-v

Date

2026-08-01

Author

Pan Li

Commit

c55a61e3cdb441909947059c5a1a4a1f8c17f34f

Source

github

Perf win

Breaking

View on GitHub →

All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: c55a61e3cdb441909947059c5a1a4a1f8c17f34f
source_type: github
headline: RISC-V: Add test cases for vwmul.vv register overlap
tldr: New test cases verify register overlap behavior for RISC-V vwmul.vv vector instructions.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector
• testing
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/c55a61e3cdb441909947059c5a1a4a1f8c17f34f
date: 2026-08-01T00:00:00.000Z

This commit adds a suite of test cases to verify the behavior of the vwmul.vv (signed widening multiply) RISC-V vector instruction when register groups overlap. The tests cover various data types and vector lengths to ensure correct operation under these specific conditions.