Landing: 93ac5163b5d0

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Project / Subsystem

gcc / arm

Date

2026-08-02

Author

Dominic P

Commit

93ac5163b5d02c2dfde88c3ec7b1f366caab9b45

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: arm
patch_id: —
commit_hash: 93ac5163b5d02c2dfde88c3ec7b1f366caab9b45
source_type: github
headline: Arm NEON intrinsics incorrectly reject zero shift amounts.
tldr: Arm NEON widening shift-left intrinsics now correctly handle zero shifts by using VMOVL.
author: Dominic P
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • arm
• neon
• intrinsics
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/93ac5163b5d02c2dfde88c3ec7b1f366caab9b45
date: 2026-08-02T00:00:00.000Z

Arm NEON widening shift-left intrinsics (vshll_n) that accept a zero shift amount were previously rejected by the assembler because the VSHLL instruction encoding does not support a zero shift. This change modifies the intrinsic to emit VMOVL for a zero shift, which has the same semantics and is correctly encoded, improving code quality for valid ACLE code. Additionally, it uses the signless form for intrinsics when the shift amount equals the element size.