Landing: a3b4c732f41f

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Project / Subsystem

gcc / arm

Date

2026-08-02

Author

Dominic P

Commit

a3b4c732f41fd627722df998ebb4c082ada20971

Source

github

Perf win

No

Breaking

No

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All attributes

project: gcc
subsystem: arm
patch_id: —
commit_hash: a3b4c732f41fd627722df998ebb4c082ada20971
source_type: github
headline: arm: Ensure acquire barrier for RELEASE/ACQUIRE CAS.
tldr: ARM atomic compare-and-swap now correctly includes an acquire barrier for RELEASE/ACQUIRE memory orders.
author: Dominic P
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • arm
• atomic
• memory model
• compiler
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/a3b4c732f41fd627722df998ebb4c082ada20971
date: 2026-08-02T00:00:00.000Z

This commit fixes a memory ordering issue on ARM for atomic compare-and-swap operations. When a success memory order of RELEASE and a failure memory order of ACQUIRE are used, the compiler previously failed to emit the necessary acquire barrier on the failure path for older ARM architectures (like ARMv6/v7) lacking specific load-acquire instructions. By removing a gate on TARGET_HAVE_LDACQ, the code now correctly promotes the memory model to ACQ_REL, ensuring both release and acquire semantics are preserved, thus resolving PR target/96056.