Landing: 48425ec4ef2a

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Project / Subsystem

gcc / aarch64

Date

2026-08-03

Author

Kyrylo Tkachov

Commit

48425ec4ef2ad3697f07a3075ff52d2d9dea91f4

Source

github

Perf win

Yes

Breaking

View on GitHub →

All attributes

project: gcc
subsystem: aarch64
patch_id: —
commit_hash: 48425ec4ef2ad3697f07a3075ff52d2d9dea91f4
source_type: github
headline: aarch64: Implement CTZ for Advanced SIMD byte and halfword modes
tldr: New AArch64 Advanced SIMD instructions for count trailing zeros (CTZ) improve performance for byte and halfword operations.
author: Kyrylo Tkachov
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• SIMD
• NEON
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/48425ec4ef2ad3697f07a3075ff52d2d9dea91f4
date: 2026-08-03T00:00:00.000Z

The AArch64 backend now implements the ctz2 instruction for Advanced SIMD’s byte and halfword modes. Previously, these modes were expanded into a less efficient generic sequence involving bit reversal, AND, CLZ, and subtraction. The new implementation directly uses RBIT and REV16 where appropriate, reducing the instruction count and eliminating the need for vector constants. This leads to faster execution for bitwise operations involving trailing zeros in these data types.