Landing: 2a696e24b6ed
Project / Subsystem
gcc / risc-v
Date
2026-08-05
Author
Pan Li
Commit
2a696e24b6ed7927c2eb0992d5dd3dd8927f1250
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 2a696e24b6ed7927c2eb0992d5dd3dd8927f1250
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vwmulsu.vv
- tldr
- RISC-V vwmulsu.vv instruction now supports register overlap, similar to other widen VV instructions.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-05T00:00:00.000Z
This commit enables register overlap for the RISC-V Vector (RVV) vwmulsu.vv instruction. By leveraging the Wvr constraint in the machine description, this change allows vwmulsu.vv to reuse registers in a manner consistent with other widening vector instructions like vwadd.vv and vwsub.vv. This enhancement is expected to improve code density and potentially performance by enabling more efficient register utilization.