Landing: 93ff238921bf
Project / Subsystem
gcc / risc-v
Date
2026-08-05
Author
Pan Li
Commit
93ff238921bf5770339fa6d4e913c55e6c588d3b
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 93ff238921bf5770339fa6d4e913c55e6c588d3b
- source_type
- github
- headline
- RISC-V: Add test cases for vwmulsu.vv register overlap
- tldr
- New test cases verify the correct handling of register overlap for the RISC-V vwmulsu.vv instruction, particularly when overlap is enabled.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-05T00:00:00.000Z
This commit adds a suite of test cases to validate the RISC-V Vector extension’s vwmulsu.vv instruction. The tests specifically focus on scenarios involving register group overlap, ensuring that the compiler correctly handles these situations when overlap is enabled. The goal is to ensure the instruction’s behavior aligns with its specification, especially concerning register allocation and usage.