Landing: 1beab80079e2

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Project / Subsystem

gcc / gcc/risc-v

Date

2026-08-12

Author

Jin Ma

Commit

1beab80079e26aac82c62452dd9217caae226c7c

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: gcc/risc-v
patch_id: —
commit_hash: 1beab80079e26aac82c62452dd9217caae226c7c
source_type: github
headline: RISC-V: Remove obsolete CACHE_ALIGNED_STD fusion
tldr: gcc: RISC-V target removes obsolete CACHE_ALIGNED_STD fusion recognizer and flag.
author: Jin Ma
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • gcc
• risc-v
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/1beab80079e26aac82c62452dd9217caae226c7c
date: 2026-08-12T00:00:00.000Z

The RISC-V backend has removed the specialized CACHE_ALIGNED_STD fusion recognizer and its associated flag. This fusion was designed for a Veyron V1 store-commit optimization that will not be implemented in silicon, and no upstream tuning options currently enable it.