Landing: 2bfe853b3b17

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Project / Subsystem

gcc / risc-v

Date

2026-08-12

Author

Peter Bergner

Commit

2bfe853b3b1703216a32a48d2bc61363140c6aea

Source

github

Perf win

No

Breaking

No

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project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 2bfe853b3b1703216a32a48d2bc61363140c6aea
source_type: github
headline: RISC-V: Add Ascalon XG CPU support
tldr: Adds support for the Ascalon XG processor core to GCC's RISC-V backend, including its specific microarchitectural features and performance characteristics.
author: Peter Bergner
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• cpu support
• gcc
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/2bfe853b3b1703216a32a48d2bc61363140c6aea
date: 2026-08-12T00:00:00.000Z

GCC’s RISC-V backend now includes support for the Ascalon XG CPU. This commit adds the necessary definitions to riscv-cores.def, riscv-opts.h, and riscv.md to recognize the tt-ascalon-xg microarchitecture. The Ascalon XG differs from the Ascalon X by lacking the zvkng extension and featuring reduced vector floating-point double-precision throughput. New defines for CPU units and reservations in tt-ascalon-d8.md capture these microarchitectural details for instruction scheduling and optimization.