Landing: 4f75092d25c0
Project / Subsystem
gcc / risc-v
Date
2026-08-12
Author
Pan Li
Commit
4f75092d25c099363892d03cb50b1142fb20bdcc
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 4f75092d25c099363892d03cb50b1142fb20bdcc
- source_type
- github
- headline
- RISC-V: Add test cases for vwmaccu.vv register overlap.
- tldr
- Adds numerous test cases for the RISC-V vwmaccu.vv vector instruction, focusing on register group overlap scenarios.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-12T00:00:00.000Z
This commit introduces a comprehensive suite of test cases for the RISC-V vwmaccu.vv vector instruction, specifically targeting register group overlap. A variety of data types (u8, u16, u32) and different mask/element counts (m1, m2, m4, mf2, mf4, mf8) are covered to ensure the instruction behaves correctly when destination and source registers overlap.