Landing: 55afdf36b7a2
Project / Subsystem
gcc / risc-v
Date
2026-08-12
Author
Pan Li
Commit
55afdf36b7a2acd881c93485ce2af6d1cf006e18
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 55afdf36b7a2acd881c93485ce2af6d1cf006e18
- source_type
- github
- headline
- RISC-V: Add test cases for vwmacc.vv register overlap.
- tldr
- Adds extensive test cases for the RISC-V vwmacc.vv vector instruction, focusing on register group overlap.
- author
- Pan Li
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testing
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-12T00:00:00.000Z
This commit adds a comprehensive set of test cases for the RISC-V vwmacc.vv vector instruction, with a particular focus on register group overlap scenarios. Tests are generated for various data types (i8, i16, i32) and configurations (m1, m2, m4, mf2, mf4, mf8) to ensure correct functionality when source and destination registers overlap.