Landing: f645deff8557

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Project / Subsystem

gcc / risc-v

Date

2026-08-14

Author

Pan Li

Commit

f645deff8557a22b3a796bec08f077cb493e7705

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: f645deff8557a22b3a796bec08f077cb493e7705
source_type: github
headline: Allow RVV register overlap for vwmaccsu.vv.
tldr: RISC-V Vector extension now allows register overlap for the vwmaccsu.vv instruction.
author: Pan Li
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vector
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/f645deff8557a22b3a796bec08f077cb493e7705
date: 2026-08-14T00:00:00.000Z

Support for register overlap has been extended to the vwmaccsu.vv instruction in the RISC-V Vector extension. Similar to other widen ternary instructions, this commit enables the reuse of vector registers for vwmaccsu.vv, which handles mixed signed and unsigned narrowed sources, improving instruction scheduling flexibility.