Landing: 8335b96b21bf
Project / Subsystem
gcc / gcc/testsuite
Date
2026-08-20
Author
Jin Ma
Commit
8335b96b21bf2866773351f906a978b8e0cf25dc
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/testsuite
- patch_id
- —
- commit_hash
- 8335b96b21bf2866773351f906a978b8e0cf25dc
- source_type
- github
- headline
- RISC-V: Fix zvl effective-target check cache collision
- tldr
- RISC-V vector length checks now use unique cache properties to avoid incorrect results.
- author
- Jin Ma
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector
- • testsuite
- • cache
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-20T00:00:00.000Z
Vector length (zvl) checks for RISC-V’s vector extension (RVV) incorrectly used a shared cache property. This could lead to unsupported tests running or supported tests being skipped because a check for one vector length (e.g., VLEN=128) might incorrectly cache results for another (e.g., VLEN=256). This change assigns a unique property to each check_runtime call for different zvl configurations, resolving the cache collision.