Landing: 60c6e44abf10
Project / Subsystem
gcc / risc-v
Date
2026-08-20
Author
Kito Cheng
Commit
60c6e44abf108088cf883aa488ec1f1dd5e7e6ce
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 60c6e44abf108088cf883aa488ec1f1dd5e7e6ce
- source_type
- github
- headline
- RISC-V: Prepare core table for identification registers
- tldr
- The RISC-V core table structure is updated to accommodate CPU identification registers.
- author
- Kito Cheng
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • compiler
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-20T00:00:00.000Z
The RISC-V core identification table structure has been modified to include space for MVENDORID, MARCHID, and MIMPID registers. Initially, these fields are set to UNKNOWN_ID for all cores, preparing the system for later population with specific CPU identification values, which is necessary for features like -mcpu=native.