Landing: af312b979a67
Project / Subsystem
gcc / risc-v
Date
2026-08-20
Author
Pan Li
Commit
af312b979a678002a97e739eaed57be605a68151
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- af312b979a678002a97e739eaed57be605a68151
- source_type
- github
- headline
- RISC-V: Allow RVV register overlap for vw{add,sub,mul}[u].vx
- tldr
- Enables RISC-V vector extension register overlap for dual-widen vx instructions like vwadd.vx.
- author
- Pan Li
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • vector extension
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-20T00:00:00.000Z
The RISC-V vector extension now allows register overlap for dual-widen vx instructions, including vwadd[u].vx, vwsub[u].vx, and vwmul[u].vx. This change leverages the ‘Wvr’ constraint in the vector configuration, potentially improving instruction scheduling and register utilization.