Landing: d3d6b2a1fba3

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Project / Subsystem

gcc / risc-v

Date

2026-08-20

Author

Kito Cheng

Commit

d3d6b2a1fba366ea71379e6564758993cb5327c8

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: d3d6b2a1fba366ea71379e6564758993cb5327c8
source_type: github
headline: RISC-V: Add CPU identification registers for 6 cores
tldr: Identification registers (MVENDORID, MARCHID, MIMPID) are added for six RISC-V cores.
author: Kito Cheng
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• cpu
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/d3d6b2a1fba366ea71379e6564758993cb5327c8
date: 2026-08-20T00:00:00.000Z

GCC’s RISC-V backend now includes the MVENDORID, MARCHID, and MIMPID identification registers for six specific RISC-V cores. This enhancement supports the automatic detection of CPU types for tuning and optimization purposes, enabling features like -mtune=native.