Landing: 7112f8883301
Project / Subsystem
gcc / RISC-V
Date
2026-08-21
Author
Kito Cheng
Commit
7112f88833018f2c5f1e07948c9c8fd4634363ed
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- RISC-V
- patch_id
- —
- commit_hash
- 7112f88833018f2c5f1e07948c9c8fd4634363ed
- source_type
- github
- headline
- Add VLEN checks to RISC-V vector tests.
- tldr
- Ensures RISC-V vector tests correctly handle varying vector lengths (VLEN).
- author
- Kito Cheng
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • RISC-V
- • vector
- • testsuite
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-08-21T00:00:00.000Z
Two RISC-V vector test cases have been updated to include stricter platform Vector Length (VLEN) checks. These tests previously ran code compiled for a 256-bit VLEN (rv64gcv_zvl256b) but only required the base riscv_v extension, causing them to fail on platforms with smaller VLENs. The tests now explicitly require specific VLEN configurations to pass, ensuring their correctness across different RISC-V vector implementations.